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? 2006 microchip technology inc. ds21428d-page 1 TC500/a/510/514 features: ? precision (up to 17 bits) a/d converter ?front end? ? 3-pin control interface to microprocessor ? flexible: user can trade-off conversion speed for resolution ? single-supply operation (tc510/tc514) ? 4 input, differential analog mux (tc514) ? automatic input voltage polarity detection ? low power dissipation: - (TC500/TC500a): 10 mw - (tc510/tc514): 18 mw ? wide analog input range: - 4.2v (TC500a/tc510) ? directly accepts bipolar and differential input signals applications: ? precision analog signal processor ? precision sensor interface ? high accuracy dc measurements general description: theTC500/a/510/514 family are precision analog front ends that implement dual slope a/d converters having a maximum resolution of 17 bits plus sign. as a minimum, each device contains the integrator, zero crossing comparator and processor interface logic. the TC500 is the base (16-bit max) device and requires both positive and negative power supplies. the TC500a is identical to the TC500 with the exception that it has improved linearity, allowing it to operate to a maximum resolution of 17 bits. the tc510 adds an on- board negative power supply converter for single- supply operation. the tc514 adds both a negative power supply converter and a 4-input differential analog multiplexer. each device has the same processor control interface consisting of 3 wires: control inputs (a and b) and zero- crossing comparator output (cmptr). the processor manipulates a, b to sequence the tc5xx through four phases of conversion: auto-zero, integrate, de-inte- grate and integrator zero. during the auto-zero phase, offset voltages in the tc5xx are corrected by a closed loop feedback mechanism. the input voltage is applied to the integrator during the integrate phase. this causes an integrator output dv/dt directly proportional to the magnitude of the input voltage. the higher the input voltage, the greater the magnitude of the voltage stored on the integrator during this phase. at the start of the de-integrate phase, an external voltage reference is applied to the integrator and, at the same time, the external host processor starts its on-board timer. the processor maintains this state until a transition occurs on the cmptr output, at which time the processor halts its timer. the resulting timer count is the converted analog data. integrator zero (the final phase of conversion) removes any residue remaining in the integrator in preparation for the next conversion. the TC500/a/510/514 offer high resolution (up to 17 bits), superior 50/60 hz noise rejection, low-power operation, minimum i/o connections, low input bias currents and lower cost compared to other converter technologies having similar conversion speeds. precision analog front ends
TC500/a/510/514 ds21428d-page 2 ? 2006 microchip technology inc. package types typical application 1 2 3 4 16 15 14 13 5 6 7 12 11 10 9 8 cmptr out a dgnd b v dd v in + v in ? v ref + buf v ss c int acom v ref ? c ref + c ref ? c az TC500/ TC500a 16-pin pdip/soic/cerdip v out ? 1 2 3 4 20 19 18 cap? 5 6 7 8 17 23 22 21 9 10 11 12 24 25 26 27 28 dgnd a b c ref ? c int c az buf acom ch4? ch3? ch2? tc514 c ref + v ref ? v ref + v dd osc cmptr out cap+ 16 15 13 14 ch1? n/c ch1+ ch2+ ch3+ ch4+ a0 a1 28-pin pdip/soic 24-pin pdip/soic 1 2 3 4 16 15 14 5 6 7 8 13 19 18 17 9 10 11 12 20 21 22 23 24 tc510 cap? dgnd a b v dd osc cmptr out v in + v in ? n/c n/c cap+ c ref ? c int c az buf acom n/c n/c n/c v out ? c ref + v ref ? v ref + level shift control logic analog switch control signals acom v ref + buf c az buffer integrator sw r sw iz cmptr 1 cmptr 2 cmptr output dgnd control logic sw 1 TC500 TC500a tc510 tc514 c ref c ref + sw r c ref - c az r int c int c int sw ri - sw ri - sw ri + sw ri - sw z sw i sw z v ss osc + + + phase decoding logic polarity detection dc-to-dc converter (tc510 & tc514) - + a b 0 0 zero integrator output 0 1 auto-zero 1 0 signal integrate 1 1 de-integrate v ref - v out - c out - 1.0 f 1.0 f v ss sw i b a a0 a1 dif. mux (tc514) ch1+ ch2+ ch3+ ch4+ ch1- ch2- ch3- ch4- cap- cap+ (TC500 TC500a) converter sate
? 2006 microchip technology inc. ds21428d-page 3 TC500/a/510/514 1.0 electrical characteristics absolute maximum ratings? tc510/tc514 positive supply voltage (v dd to gnd) ......................................... +10.5v TC500/TC500a supply voltage (v dd to v ss ) .............................................. +18v TC500/TC500a positive supply voltage (v dd to gnd) ............................................ +12v TC500/TC500a negative supply voltage (v ss to gnd)................................................-8v analog input voltage (v in + or v in -) ............v dd to v ss logic input voltage...............v dd +0.3v to gnd - 0.3v voltage on osc: ........................... -0.3v to (v dd +0.3v) for v dd < 5.5v ambient operating temperature range: ................................................................ 0c to +70c storage temperature range: ............. -65c to +150c ? stresses above those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics electrical specifications: unless otherwise specified, tc510/tc514 : v dd = +5v, TC500/TC500a : v ss = 5v. c az = c ref = 0.47 f. parameters sym t a = +25c t a = 0c to 70c units conditions min. typ. max. min. typ. max. analog resolution 60 ? ? ? ? ? v note 1 zero-scale error with auto-zero phase zse ? ? 0.005 ? 0.005 0.012 % f.s. TC500/tc510/tc514 ? ? 0.003 ? 0.003 0.009 TC500a end point linearity enl ? 0.005 0.015 ? 0.015 0.060 % f.s. TC500/tc510/tc514 ? ? 0.010 ? 0.010 0.045 % f.s. note 1 , note 2 , TC500a best-case straight line linearity nl ? 0.003 0.008 ? ? ? % f.s. TC500/tc510/tc514 , note 1 , note 2 ? ? 0.005 ? ? ? % f.s. TC500a zero-scale temp. coefficient zs tc ??? ?1 2 v/c over operating temperature range full-scale symmetry error (rollover error) sye ? 0.01 ? ? 0.03 ? % f.s. note 1 full-scale temperature coefficient fs tc ? ? ? ? 10 ? ppm/c over operating temperature range; external reference tc = 0 ppm/c input current i in ?6? ??? pav in = 0v common mode voltage range v cmr v ss + 1.5 ? v dd ? 1.5 v ss + 1.5 ? v dd ? 1.5 v integrator output swing v ss + 0.9 ? v dd ? 0.9 v ss + 0.9 ? v ss + 0.9 v analog input signal range v ss + 1.5 ? v dd ? 1.5 v ss + 1.5 ? v ss + 1.5 v acom = gnd = 0v note 1: integrate time 66 msec, auto-zero time 66 msec, v int (peak) 4v. 2: end point linearity at 1/4, 1/2, 3/4 f.s. after full-scale adjustment. 3: rollover error is related to c int , c ref , c az characteristics.
TC500/a/510/514 ds21428d-page 4 ? 2006 microchip technology inc. voltage reference range v ref v ss +1 ? v dd ? 1 v ss +1 ? v dd ? 1 v v ref - v ref + digital comparator logic 1 , output high v oh 4? ? 4 ? ? vi source = 400 a comparator logic 0 , output low v ol ? ? 0.4 ? ? 0.4 v i sink = 2.1 ma logic 1 , input high voltage v ih 3.5 ? ? 3.5 ? ? v logic 0 , input low voltage v il ?? 1 ? ? 1 v logic input current i l ?? ? ? 0.3 a logic ? 1 ? or ? 0 ? comparator delay t d ?2 ? ? 3? sec multiplexer (tc514 only) maximum input voltage -2.5 ? 2.5 -2.5 ? 2.5 v v dd = 5v drain/source on resistance r dson ? 6 10 ? ? ? k v dd = 5v power (tc510/tc514 only) supply current i s ? 1.8 2.4 ? ? 3.5 ma v dd = 5v, a = 1, b = 1 power dissipation p d ?18? ? ? ?mwv dd = 5v positive supply operating voltage range v dd 4.5 ? 5.5 4.5 ? 5.5 v operating source resistance r out ? 60 85 ? ? 100 i out = 10 ma oscillator frequency ? 100 ? ? ? ? khz note 1 maximum current out i out ? ? -10 ? ? -10 ma v dd = 5v power (TC500/TC500a only) supply current i s ? 1 1.5 ? ? 2.5 ma v s = 5v, a = b = 1 power dissipation p d ?10? ? ? ?mwv dd = 5v, v ss = -5v positive supply operating range v dd 4.5 ? 7.5 4.5 ? 7.5 v negative supply operating range v ss -4.5 ? -7.5 - 4.5 ? -7.5 v dc characteristics (continued) electrical specifications: unless otherwise specified, tc510/tc514 : v dd = +5v, TC500/TC500a : v ss = 5v. c az = c ref = 0.47 f. parameters sym t a = +25c t a = 0c to 70c units conditions min. typ. max. min. typ. max. note 1: integrate time 66 msec, auto-zero time 66 msec, v int (peak) 4v. 2: end point linearity at 1/4, 1/2, 3/4 f.s. after full-scale adjustment. 3: rollover error is related to c int , c ref , c az characteristics.
? 2006 microchip technology inc. ds21428d-page 5 TC500/a/510/514 2.0 typical performance curves figure 2-1: output voltage vs. load current. figure 2-2: output ripple vs. load current. figure 2-3: oscillator frequency vs. capacitance. figure 2-4: output voltage vs. output current. figure 2-5: output source resistance vs. temperature. figure 2-6: oscillator frequency vs. temperature. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. load current (ma) -5 -4 -3 -2 -1 0 1 2 3 4 5 010 20 30 40 50 60 70 80 output voltage (v) t a = +25 c v+ = 5v slope 60 load current (ma) 0 3 456 12 78 910 0 25 50 75 100 125 150 175 200 output ripple (mv pk-pk) v+ = 5v, t a = +25c osc. freq. = 100 khz cap = 1 f cap = 10 f oscillator capacitance (pf) 100 10 1 110 100 1000 oscillator frequency (khz) t a = +25c v+ = 5v output current (ma) 06810 4 2141618 12 20 -0 -1 -3 -2 -4 -5 -7 -6 -8 output voltage (v) t a = +25 c temperature ( c) 70 80 90 100 60 50 40 -50 025 -25 50 75 100 output source resistance ( ) v+ = 5v i out = 10 ma temperature (c) 125 150 100 75 50 -50 025 -25 50 75 125 100 oscillator frequency (khz) v+ = 5v
TC500/a/510/514 ds21428d-page 6 ? 2006 microchip technology inc. 3.0 pin descriptions the descriptions of the pins are listed in table 3-1. table 3-1: pin function table pin no. symbol function TC500, TC500a tc510 tc514 12 2c int integrator output. integrator capacitor connection. 2 not used not used v ss negative power supply input (TC500/TC500a only). 33 3c az auto-zero input. the auto-zero capacitor connection. 4 4 4 buf buffer output. the integrator capacitor connection. 5 5 5 acom this pin is grounded in most applications. it is recommended that acom and the input common pin (ve n - or ch n -) be within the analog common mode range (cmr). 66 6c ref - input. negative reference capacitor connection. 77 7c ref + input. positive reference capacitor connection. 88 8v ref - input. external voltage reference (-) connection. 99 9v ref + input. external voltage reference (+) connection. 10 15 not used v in - negative analog input. 11 16 not used v in + positive analog input. 12 18 22 a input. converter phase control msb. (see input b.) 13 17 21 b input. converter phase control lsb. the states of a, b place the tc5xx in one of four required phases. a c onversion is complete when all four phases have been executed: phase control input pins: ab = 00: integrator zero 01: auto-zero 10: integrate 11: de-integrate 14 19 23 cmptr out zero crossing comparator output. cmptr is high during the integration phase when a positive input voltage is being integrated and is low when a negative input voltage is being integrated. a high-to-low transiti on on cmptr signals the processor that the de-integrate phase is completed. cmptr is undefined during the auto-zero phase. it should be monitored to time the integrator zero phase. 15 23 27 dgnd input. digital ground. 16 21 25 v dd input. power supply positive connection. ? 22 26 cap+ input. negative power supply converter capacitor (+) connection. ? 24 28 cap- input. negative power supply converter capacitor (-) connection. ?1 1v out - output. negative power supply converter output and reservoir capacitor connection. this output can be used to power other devices in the circuit requiring a negative bias voltage. ? 20 24 osc oscillator control input. the negative power supply converter normally runs at a frequency of 100 khz. the converter o scillator frequency can be slowed down (to reduce quiescent current) by connecting an external capacitor between this pin and v dd (see section 2.0 ?typical performance curves? ). ? ? 18 ch1+ positive analog input pin. mux channel 1. ? ? 13 ch1- negative analog input pin. mux channel 1. ? ? 17 ch2+ positive analog input pin. mux channel 2. ? ? 12 ch2- negative analog input pin. mux channel 2. ? ? 16 ch3+ positive analog input pin. mux channel 3. ? ? 11 ch3- negative analog input pin. mux channel 3. ? ? 15 ch4+ positive analog input pin. mux channel 4. ? ? 10 ch4- negative analog input pin. mux channel 4 ? ? 20 a0 multiplexer input channel select input lsb (see a1). ? ? 19 a1 multiplexer input channel select input msb. phase control input pins: a1, a0 = 00 = channel 1 01 = channel 2 10 = channel 3 11 = channel 4
? 2006 microchip technology inc. ds21428d-page 7 TC500/a/510/514 4.0 detailed description 4.1 dual slope conversion principles actual data conversion is accomplished in two phases: input signal integration and reference voltage de-integration. the integrator output is initialized to 0v prior to the start of integration. during integration, analog switch s 1 con- nects v in to the integrator input where it is maintained for a fixed time period (t int ). the application of v in causes the integrator output to depart 0v at a rate deter- mined by the magnitude of v in and a direction deter- mined by the polarity of v in . the de-integration phase is initiated immediately at the expiration of t int . during de-integration, s1 connects a reference voltage (having a polarity opposite that of v in ) to the integrator input. at the same time, an external precision timer is started. the de-integration phase is maintained until the comparator output changes state, indicating the integrator has returned to its starting point of 0v. when this occurs, the precision timer is stopped. the de- integration time period (t deint ), as measured by the precision timer, is directly proportional to the magnitude of the applied input voltage (see figure 4-3). a simple mathematical equation relates the input signal, reference voltage and integration time: equation 4-1: for a constant v in : equation 4-2: the dual slope converter accuracy is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. an inherent benefit is noise immunity. input noise spikes are integrated (averaged to zero) during the integration periods. integrating adcs are immune to the large conversion errors that plague successive approximation converters in high noise environments. integrating converters provide inherent noise rejection with at least a 20db/decade attenuation rate. interference signals with frequencies at integral multiples of the integration period are, theoretically, completely removed, since the average value of a sine wave of frequency (1/t) averaged over a period (t) is zero. integrating converters often establish the integration period to reject 50/60 hz line frequency interference signals. the ability to reject such signals is shown by a normal mode rejection plot (figure 4-1). normal mode rejection is limited in practice to 50 to 65 db, since the line frequency can deviate by a few tenths of a percent (figure 4-2). figure 4-1: integrating converter normal mode rejection. figure 4-2: line frequency deviation. where: v ref = reference voltage t int = signal integration time (fixed) t deint = reference voltage integration time (variable ) 1 r int c int ----------------------- - v in t () dt 0 t int v ref c deint r int c int -------------------------------- = v in v ref t deint t int ----------------- - = 30 20 10 0 0.1/t 1/t 10/t input frequency normal mode rejection (db) t = measurment period 0.01 0.1 1.0 normal mode rejeciton (db) 80 70 60 50 40 30 20 t = 0.1 sec line frequency deviation from 60 hz (%) normal mode rejection = 20 log dev = deviation from 60 hz t = integration period sin 60 t (1 ) p p dev 100 dev 100 60 t (1 )
TC500/a/510/514 ds21428d-page 8 ? 2006 microchip technology inc. figure 4-3: basic dual slope converter. phase control comparator integrator output integrator c int analog input (v in ) switch driver ref voltage control logic polarity control s 1 i/o timer counter rom ram microcomputer ab cmptr out v supply t int tc510 v int v in v ref v in 1/2 v ref t deint ? + r int v int ? +
? 2006 microchip technology inc. ds21428d-page 9 TC500/a/510/514 5.0 TC500/a/510/514 converter operation the TC500/a/510/514 incorporates an auto-zero and integrator phase in addition to the input signal integrate and reference de-integrate phases. the addition of these phases reduce system errors, calibration steps and shorten overrange recovery time. a typical measurement cycle uses all four phases in the following order: 1. auto-zero. 2. input signal integration. 3. reference de-integration. 4. integrator output zero. the internal analog switch status for each of these phases is summarized in table 5-1. this table references the typical application. table 5-1: internal analog gate status 5.1 auto-zero phase (az) during this phase, errors due to buffer, integrator and comparator offset voltages are nulled out by charging c az (auto-zero capacitor) with a compensating error voltage. the external input signal is disconnected from the internal circuitry by opening the two sw i switches. the internal input points connect to analog common. the reference capacitor is charged to the reference voltage potential through sw r . a feedback loop, closed around the integrator and comparator, charges the capacitor (c az ) with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages. 5.2 analog input signal integration phase (int) the tc5xx integrates the differential voltage between the v in + and v in ? inputs. the differential voltage must be within the device?s common mode range v cmr . the input signal polarity is normally checked via software at the end of this phase: cmptr = 1 for positive polarity; cmptr = 0 for negative polarity. 5.3 reference voltage de-integration phase (d int ) the previously charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero. an externally-provided, precision timer is used to measure the duration of this phase. the resulting time measurement is proportional to the magnitude of the applied input voltage. 5.4 integrator output zero phase (iz) this phase ensures the integrator output is at 0v when the auto-zero phase is entered, and that only system offset voltages are compensated. this phase is used at the end of the reference voltage de-integration phase and must be used for all tc5xx applications having resolutions of 12-bits or more. if this phase is not used, the value of the auto-zero capacitor (c az ) must be about 2 to 3 times the value of the integration capacitor (c int ) to reduce the effects of charge sharing. the inte- grator output zero phase should be programmed to operate until the output of the comparator returns high. the overall timing system is shown in figure 5-1. conversion phase sw i sw r +sw r -sw z sw r sw 1 sw iz auto-zero (a = 0, b = 1) ? ? ? closed closed closed ? input signal integration (a = 1, b = 0) closed ? ? ? ? ? ? reference voltage de-integration (a =1, b = 1) ? * closed ? ? ? closed ? integrator output zero (a = 0, b = 0) ? ? ? ? closed closed closed * assumes a positive polarity input signal. sw ? ri would be closed for a negative input signal.
TC500/a/510/514 ds21428d-page 10 ? 2006 microchip technology inc. figure 5-1: typical dual slope a/d converter system timing. auto-zero integrate full-scale input reference de-integrate overshoot integrator output zero converter status t time integrator voltage v int comparator output ab inputs controller operation notes: comparator delay begin conversion with auto-zero phase (positive input shown) sample input polarity the length of this phase is chosen almost arbitrarily but needs to be long enough to null out worst case errors (see text). minimizing overshoot will minimize i.o.z. time ready for next conversion (auto-zero is idle state) time input integration phase capture de-integration time integrator output zero phase complete undefined a = 0 b = 1 a = 1 0 for negative input 1 for positive input b = 0 b = 1 b = 0 a = 1 a = 0 typically = t int t int 0 a b comparator delay + processor latency
? 2006 microchip technology inc. ds21428d-page 11 TC500/a/510/514 6.0 analog section 6.1 differential inputs (v in + , v in ?) the tc5xx operates with differential voltages within the input amplifier common mode range. the amplifier common mode range extends from 1.5v below positive supply to 1.5v above negative supply. within this common mode voltage range, common mode rejection is typically 80 db. full accuracy is maintained, however, when the inputs are no less than 1.5v from either supply. the integrator output also follows the common mode voltage. the integrator output must not be allowed to saturate. a worst-case condition exists, for example, when a large, positive common mode voltage, with a near full-scale negative differential input voltage, is applied. the negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. for these critical applications, the integrator swing can be reduced. the integrator output can swing within 0.9v of either supply without loss of linearity. 6.2 analog common analog common is used as v in return during system zero and reference de-integrate. if v in ? is different from analog common, a common mode voltage exists in the system. this signal is rejected by the excellent cmr of the converter. in most applications, v in ? will be set at a fixed known voltage (i.e., power supply common). a common mode voltage will exist when v in ? is not connected to analog common. 6.3 differential reference (v ref + , v ref ?) the reference voltage can be anywhere within 1v of the power supply voltage of the converter. rollover error is caused by the reference capacitor losing or gaining charge due to stray capacitance on its nodes. the difference in reference for (+) or (-) input voltages will cause a rollover error. this error can be minimized by using a large reference capacitor in comparison to the stray capacitance. 6.4 phase control inputs (a, b) the a, b unlatched logic inputs select the tc5xx operating phase. the a, b inputs are normally driven by a microprocessor i/o port or external logic. 6.5 comparator output by monitoring the comparator output during the fixed signal integrate time, the input signal polarity can be determined by the microprocessor controlling the conversion. the comparator output is high for positive signals and low for negative signals during the signal integrate phase (see figure 6-1). during the reference de-integrate phase, the comparator output will make a high-to-low transition as the integrator output ramp crosses zero. the transition is used to signal the processor that the conversion is complete. the internal comparator delay is 2 sec, typically. figure 6-1 shows the comparator output for large positive and negative signal inputs. for signal inputs at or near zero volts, however, the integrator swing is very small. if common mode noise is present, the comparator can switch several times during the beginning of the signal integrate period. to ensure that the polarity reading is correct, the comparator output should be read and stored at the end of the signal integrate phase. the comparator output is undefined during the auto- zero phase and is used to time the integrator output zero phase. (see section 8.6 ?integrator output zero phase? ). figure 6-1: comparator output. integrator output zero crossing comparator output reference signal integrate integrator output zero crossing comparator output reference deintegrate signal integrate b. negative input signal a. positive input signal de-integrate
TC500/a/510/514 ds21428d-page 12 ? 2006 microchip technology inc. 7.0 typical applications 7.1 component value selection the procedure outlined below allows the user to arrive at values for the following tc5xx design variables: 1. integration phase timing. 2. integrator timing components (r int , c int ). 3. auto-zero and reference capacitors. 4. voltage reference. 7.2 select integration time integration time must be picked as a multiple of the period of the line frequency. for example, t int times of 33 msec, 66 msec and 132 msec maximize 60 hz line rejection. 7.3 dint and iz phase timing the duration of the dint phase is a function of the amount of voltage stored on the integrator during t int and the value of v ref . the dint phase must be initiated immediately following int and terminated when an inte- grator output zero-crossing is detected. in general, the maximum number of counts chosen for dint is twice that of int (with v ref chosen at v in(max) /2). 7.4 calculate integrating resistor (r int ) the desired full-scale input voltage and amplifier output current capability determine the value of r int . the buffer and integrator amplifiers each have a full-scale current of 20 a. the value of r int is, therefore, directly calculated in the following equation: equation 7-1: 7.5 select reference (c ref ) and auto- zero (c az ) capacitors c ref and c az must be low leakage capacitors (such as polypropylene). the slower the conversion rate, the larger the value c ref must be. recommended capacitors for c ref and c az are shown in table 7-1. larger values for c az and c ref may also be used to limit rollover errors. table 7-1: c ref and c az selection 7.6 calculate integrating capacitor (c int ) the integrating capacitor must be selected to maximize integrator output voltage swing. the integrator output voltage swing is defined as the absolute value of v dd (or v ss ) less 0.9v (i.e., iv dd - 0.9vi or iv ss + 0.9vi). using the 20 a buffer maximum output current, the value of the integrating capacitor is calculated using the following equation. equation 7-2: it is critical that the integrating capacitor has a very low dielectric absorption. polypropylene capacitors are an example of one such dialectic. polyester and poly- bicarbonate capacitors may also be used in less critical applications. table 7-2 summarizes recommended capacitors for c int . table 7-2: recommended capacitor for c int 7.7 calculate v ref the reference de-integration voltage is calculated using the following equation: equation 7-3: where: v in(max) = maximum input voltage (full count voltage ) r int = integrating resistor (in m ) for loop stability, r int should be 50 k . r int in m () v in max () 20 ---------------------- - = conversions per second typical value of c ref , c az ( f) suggested* part number >7 0.1 smr5 104k50j01l4 2 to 7 0.22 smr5 224k50j02l4 2 or less 0.47 smr5 474k50j04l4 * manufactured by evox rifa, inc. value suggested part number* 0.1 smr5 104k50j01l4 0.22 smr5 224k50j02l4 0.33 smr5 334k50j03l4 0.47 smr5 474k50j04l4 * manufactured by evox rifa, inc. where: t int = integration period v s = iv dd i or iv ss i, whichever is less (TC500/a) v s = iv dd i (tc510, tc514) c int t int () 20 10 6 ? () v s 0.9 ? () -------------------------------------------- - = v ref v s 0.9 ? () c int () r int () 2r int () ---------------------------------------------------------- - v =
? 2006 microchip technology inc. ds21428d-page 13 TC500/a/510/514 8.0 design considerations 8.1 noise the threshold noise (n th ) is the algebraic sum of the integrator and comparator noise and is typically 30 v. figure 8-1 illustrates how the value of the reference voltage can affect the final count. such errors can be reduced by increased integration times, in the same way that 50/60 hz noise is rejected. the signal-to- noise ratio is related to the integration time (t int ) and the integration time constant (r int , c int ) as follows: equation 8-1: 8.2 system timing to obtain maximum performance from the tc5xx, the overshoot at the end of the de-integration phase must be minimized. also, the integrator output zero phase must be terminated as soon as the comparator output returns high (see figure 5-1). figure 5-1 shows the overall timing for a typical system in which a tc5xx is interfaced to a microcontroller. the microcontroller drives the a, b inputs with i/o lines and monitors the comparator output (cmptr) using an i/o line or dedicated timer capture control pin. it may be necessary to monitor the state of the cmptr output in addition to having it control a timer directly for the reference de-integration phase (this is further explained below.) the timing diagram in figure 5-1 is not to scale, as the timing in a real system depends on many system parameters and component value selections. there are four critical timing events (as shown in figure 5-1): sampling the input polarity, capturing the de-integration time, minimizing overshoot and properly executing the integrator output zero phase. 8.3 auto-zero phase the length of this phase is usually set to be equal to the input signal integration time. this decision is virtually arbitrary since the magnitudes of the various system errors are not known. setting the auto-zero time equal to the input integrate time should be more than adequate to null out system errors. the system may remain in this phase indefinitely (i.e., auto-zero is the appropriate idle state for a tc5xx device). 8.4 input signal integrate phase the length of this phase is constant from one conversion to the next and depends on system parameters and component value selections. the calculation of t int is shown elsewhere in this data sheet. at some point near the end of this phase, the microcontroller should sample cmptr to determine the input signal polarity. this value is, in effect, the sign bit for the overall conversion result. optimally, cmptr should be sampled just before this phase is terminated by changing ab from 10 to 11. the consideration here is that, during the initial stage of input integration when the integrator voltage is low, the comparator may be affected by noise and its output unreliable. once integration is well underway, the comparator will be in a defined state. 8.5 reference de-integration the length of this phase must be precisely measured from the transition of ab from 10 to 11 to the falling- edge of cmptr. the comparator delay contributes some error in timing this phase. the typical delay is specified to be 2 sec. this should be considered in the context of the length of a single count when determining overall system performance and possible single count errors. additionally, overshoot will result in charge accumulating on the integrator once its output crosses zero. this charge must be nulled during the integrator output zero phase. s/n (db) 20 log v in 30 10 6 ? ---------------------- - t int r int () c int () ? --------------------------------------- ? ?? ?? ?? =
TC500/a/510/514 ds21428d-page 14 ? 2006 microchip technology inc. figure 8-1: noise threshold. 8.6 integrator output zero phase the comparator delay and the controller?s response latency may result in overshoot, causing charge buildup on the integrator at the end of a conversion. this charge must be removed or performance will degrade. the integrator output zero phase should be activated (ab = 00 ) until cmptr goes high. it is absolutely critical that this phase be terminated immediately so that overshoot is not allowed to occur in the opposite direction. at this point, it can be assured that the integrator is near zero. auto-zero should be entered (ab = 01 ) and the tc5xx held in this state until the next cycle is begun (see figure 8-2). figure 8-2: overshoot. 8.7 using the tc510/tc514 8.7.1 negative supply voltage converter (tc510, tc514) a capacitive charge pump is employed to invert the voltage on v dd for negative bias within the tc510/ tc514. this voltage is also available on the v out - pin to provide negative bias elsewhere in the system. two external capacitors are required to perform the conversion. timing is generated by an internal state machine driven from an on-board oscillator. during the first phase, capacitor c f is switched across the power supply and charged to v s +. this charge is transferred to capacitor c out - during the second phase. the oscillator normally runs at 100 khz to ensure minimum output ripple. this frequency can be reduced by placing a capacitor from osc to v dd . the relationship between the capacitor value is shown in section 2.0 ?typical performance curves? . 8.7.2 analog input multiplexer (tc514) the tc514 is equipped with a four-input differential analog multiplexer. input channels are selected using select inputs (a1, a0). these are high-true control signals (i.e., channel 0 is selected when (a1, a0 = 00 ). low v ref normal v ref high v ref s n th s n th 30v s n th slope (s) = n th = noise threshold v ref r int c int integrator output comparator output comp integrate phase de-integrate phase integrator zero phase zero crossing overshoot
? 2006 microchip technology inc. ds21428d-page 15 TC500/a/510/514 9.0 design examples refer to figures 9-1 to 9-4. equation 9-1: given: required resolution: 16 bits (65,536 counts). maximum v in : 2v power supply voltage: +5v 60 hz system step 1. pick integration time (t int ) as a multiple of the line frequency: 1/60 hz = 16.6 msec. use 4x line frequency. = 66 msec step 2. calculate r int : r int = v in(max) /20 a 2 /20 a = 100 k step 3. calculate c int for maximum (4v) integrator output swing. c int = (t int ) (20 x 10 ?6 ) / (v s - 0.9) = (.066) (20 x 10 ?6 ) / (4.1) = 0.32 f (use closest value: 0.33 f) note: microchip recommended capacitor: evox rifa p/n: 5mr5 334k50j03l4. step 4. choose c ref and c az based on conversion rate. conversions/sec: = 1/(t az + t int + 2 t int + 2 msec) = 1/(66 msec +66 msec +132 msec +2 msec) = 3.7 conversions/sec from which c az = c ref = 0.22 f (see table 7-1) note: microchip recommended capacitor: evox rifa p/n: 5mr5 224k50j02l4 step 5. calculate v ref : v ref v s 0.9 ? () c int () r int () 2t int () ---------------------------------------------------------- - = 4.1 () 0.33 1 6 ? () 10 5 () = 20.66 () -------------------------------------------------------------- 1.025 =
TC500/a/510/514 ds21428d-page 16 ? 2006 microchip technology inc. figure 9-1: tc510 design sample. figure 9-2: tc514 design example. input+ input- +5v +5v pin 2 pin 19 pin 2 pin 19 c int 0.33 f v in + typical waveform s 1 f 1 f c az 0.22 f c ref v in - r int 100 k 1 2 3 4 16 15 cap- 5 6 7 9 19 18 17 8 21 22 23 24 dgnd v ref + v out - a b c ref - c int c az buf acom tc510 v ref - v in + v in - cap+ v dd cmptr 0.22 f c1 0.01 f r 2 10 k +5v r3, 10 k mcp1525 1 f c ref + microcontroller picmicro ? +5v +5v pin 2 pin 23 pin 2 pin 23 v in + typical waveforms 1 f v in - cap- 23 22 21 25 26 27 28 dgnd a b tc514 cap+ v dd cmptr analog mux logic input 1+ input 1- input 2+ input 2- input 3+ input 3- input4+ input4- 18 13 a1 ch1+ 17 12 ch2+ ch2- 16 11 ch3+ ch3- 15 10 ch4+ ch4- 22 19 a0 ch1- c int 0.33 f 1 f c az 0.22 f c ref r int 100 k 1 2 3 4 5 6 7 9 8 v ref + v out - c ref - c int c az buf acom v ref - 0.22 f c1 0.01 f r 2 10 k +5v r3, 10 k mcp1525 1 f c ref + microcontroller picmicro ?
? 2006 microchip technology inc. ds21428d-page 17 TC500/a/510/514 figure 9-3: tc510 to ibm ? compatible printer port. pc printer port port 0378 hex input + +5v 10 k 10 k 100 k 100 k 1 f 1 f 1 21 2 2 3 3 4 16 15 cap- 5 6 7 8 19 10 18 17 9 22 23 24 dgnd v out - v dd a b c int c az buf acom tc510 c ref + v in + cap+ cmptr 0.22 f 0.22 f 0.01 f 0.01 f 1 f 0.33 f mcp1525 c ref - v ref + v ref - v in - ?
TC500/a/510/514 ds21428d-page 18 ? 2006 microchip technology inc. figure 9-4: tc514 to ibm ? compatible printer port. ibm ? printer port port 0378 hex +5v 10 k 100 k 1 f 1 f 1 25 2 2 3 3 4 cap? 5 6 7 8 23 10 22 21 9 26 27 28 dgnd v out v dd a b c ref + tc514 buf 0.22 f 10 k 10 k 0.22 f 0.01 f 0.33 f ch1+ input 1 + 18 ? 13 input 2 + 17 ? 12 input 3 + 16 ? 11 input 4 + 15 ? 10 cap+ c ref - v ref + v ref - c az c int acom ch1? ch2+ ch2? ch3+ ch3? ch4+ ch4? cmptr analog mux control logic a0 a1 20 19 mcp1525
? 2006 microchip technology inc. ds21428d-page 19 TC500/a/510/514 10.0 packaging information 10.1 package marking information 16-lead pdip (300 mil) example: 16-lead soic (300 mil) example: xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn xxxxxxxxxxxxx yywwnnn TC500 cpe 0441256 xxxxxxxxxxxxx TC500 acoe 0441256 legend: xx...x customer specific information * yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for cus- tomer specific information. * standard marking consists of microchip part number, year code, week code, traceability code. for marking beyond this, certain price adders apply. please check with your microchip sales office. 16-lead cerdip (300 mil) example: xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn TC500 aije 0441256
TC500/a/510/514 ds21428d-page 20 ? 2006 microchip technology inc. package marking information (continued) 28-lead pdip (300 mil) example: 28-lead soic (300 mil) example: xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn tc514 cpj 0441256 xxxxxxxxxxxxx yywwnnn xxxxxxxxxxxxx xxxxxxxxxxxxx 0441256 tc514 coi 24-lead pdip (300 mil) example: 24-lead soic (300 mil) example: yywwnnn xxxxxxxxxxxxx 0441256 tc510 cpf xxxxxxxxxxxxx yywwnnn xxxxxxxxxxxxx 0441256 tc510 cog
? 2006 microchip technology inc. ds21428d-page 21 TC500/a/510/514 16-lead ceramic dual in-line (je) ? 300 mil (cerdip) 10 .4 1 9 . 1 4 8 . 25 .4 10 . 360 . 325 eb overa ll ro w spac i ng 0 . 53 0 .4 6 0 . 38 . 021 . 018 . 015 b l o w er l ead wi dt h 1 . 65 1 .4 0 1 . 1 4 . 065 . 055 . 0 4 5 b1 upper l ead wi dt h 0 . 36 0 . 30 0 . 20 . 01 4 . 012 . 008 c l ead thi ckness 5 . 08 4. 1 4 3 . 18 . 200 . 163 . 125 l ti p to seat i ng p l ane 19 . 81 19 . 30 19 . 10 . 780 . 760 . 752 d overa ll l engt h 7 . 52 7 . 32 7 . 11 . 296 . 288 . 280 e 1 ceram i c pkg . wi dt h 8 . 25 7 . 75 7 . 37 . 325 . 305 . 290 e s h ou l der to s h ou l der wi dt h 1 . 02 0 . 76 0 . 38 . 0 4 0 . 030 . 015 a1 standoff 5 . 08 4. 57 4. 06 . 200 . 180 . 160 a t op to seat i ng p l ane 2 . 5 4 . 100 p p i tc h 18 18 n n um b er of p i ns ma x n om m in ma x n om m in d i mens i on li m i ts m illi m ete rs in c he s * un i ts j e d e c e qu i va l ent : ms - 030 dra wi ng n o . c0 4- 003 * contro lli ng parameter 1 2 d n e 1 c eb e p l a2 b b1 a a1
TC500/a/510/514 ds21428d-page 22 ? 2006 microchip technology inc. 16-lead plastic dual in-line (pe) ? 300 mil (pdip) 2 1 d n e1 c eb e p l a2 b b1 a a1 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 .036 .022 .018 .014 b lower lead width 1.78 1.46 1.14 .070 .058 .045 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 19.30 19.05 18.80 .760 .750 .740 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 16 16 n number of pins max nom min max nom min dimension limits millimeters inches * units dimensions d and e1 do not include mold flash or protrusions. mo ld flash or protrusions shall not exceed .010" (0.254mm) per s ide. notes : jedec equivalent: ms-001 revised 07-21-05 * controlling parameter drawing no. c04-017
? 2006 microchip technology inc. ds21428d-page 23 TC500/a/510/514 16-lead plastic small outline (oe) ? wide, 300 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 10.49 10.30 10.10 .413 .406 .398 d overall length 7.59 7.49 7.39 .299 .295 .291 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 16 16 n number of pins max nom min max nom min dimension limits millimeters inches * units l c h 45 1 2 d p n b e1 e a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: ms-013 drawing no. c04-102 significant characteristic
TC500/a/510/514 ds21428d-page 24 ? 2006 microchip technology inc. 24-lead skinny plastic dual in-line (pf) ? 300 mil (pdip) a2 2 1 d n e1 c eb e p l b b1 a a1 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.52 1.33 1.14 .060 .053 .045 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.30 3.18 3.05 .130 .125 .120 l tip to seating plane 31.88 31.75 31.62 1.255 1.250 1.245 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.87 7.49 .325 .310 .295 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 24 24 n number of pins max nom min max nom min dimension limits millimeters inches * units dimensions d and e1 do not include mold flash or protrusions. mo ld flash or protrusions shall not exceed .010" (0.254mm) per s ide. notes: jedec equivalent: ms-001 af drawing no. c04-043 * controlling parameter revised 09-14-05
? 2006 microchip technology inc. ds21428d-page 25 TC500/a/510/514 24-lead plastic small outline (og) ? wide, 300 mil (soic) 2 1 d e n b e e1 l c h a2 a a1 h foot angle 0 8 0 8 15 5 15 5 mold draft angle bottom 15 5 15 5 mold draft angle top 0.51 0.31 .020 .012 b lead width 0.33 0.20 .013 .008 c lead thickness 1.27 0.40 .050 .016 l foot length 0.75 0.25 .030 .010 h chamfer distance 15.40 bsc .607 bsc d overall length 7.50 bsc .295 bsc e1 molded package width 10.30 bsc .406 bsc e overall width 0.30 0.10 .012 .004 a1 standoff 2.55 2.05 .100 .081 a2 molded package thickness 2.65 2.35 .104 .093 a overall height 1.27 bsc .050 bsc e pitch 24 24 n number of pins max nom min max nom min dimension limits millimeters * inches units dimensions d and e1 do not include mold flash or protrusions. mo ld flash or protrusions shall not exceed .010" (0.254mm) per s ide. notes: jedec equivalent: ms-013 ad revised 07-19-05 * controlling parameter per jedec ms-103 revision c. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- bsc: basic dimension. theoretically exact value shown without tolerances. see asme y14.5m drawing no. c04-025
TC500/a/510/514 ds21428d-page 26 ? 2006 microchip technology inc. 28-lead skinny plastic dual in-line (pj) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches * units 2 1 d n e1 c eb e p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per sid e. significant characteristic
? 2006 microchip technology inc. ds21428d-page 27 TC500/a/510/514 28-lead plastic small outline (oi) ? wide, 300 mil (soic) foot angle top 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches * units 2 1 d p n b e e1 l c 45 h a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic
TC500/a/510/514 ds21428d-page 28 ? 2006 microchip technology inc. 10.2 product tape and reel specifications component taping orientation for 16-pin soic (wide) devices w pin 1 user direction of feed standard reel component orientation for 713 suffix device p package carrier width (w) pitch (p) part per full reel reel size 16-pin soic ( w ) 16 mm 12 mm 1000 13 in carrier tape, number of components per reel and reel size component taping orientation for 24-pin soic (wide) devices pin 1 user direction of feed standard reel component orientation for 713 suffix device w p package carrier width (w) pitch (p) part per full reel reel size 24-pin soic ( w ) 24 mm 12 mm 1000 13 in carrier tape, number of components per reel and reel size
? 2006 microchip technology inc. ds21428d-page 29 TC500/a/510/514 product tape and reel specifications (continued) component taping orientation for 28-pin soic (wide) devices pin 1 user direction of feed standard reel component orientation for 713 suffix device w p package carrier width (w) pitch (p) part per full reel reel size 28-pin soic ( w ) 24 mm 12 mm 1000 13 in carrier tape, number of components per reel and reel size
TC500/a/510/514 ds21428d-page 30 ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. ds21428d-page 31 TC500/a/510/514 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . sales and support part no. x /xx package temperature range device device TC500 16 bit analog processor TC500a 16 bit analog processor tc510 precision analog front end tc514 precision analog front end temperature range c = 0c to +70c (commercial) i = -25c to +85c (industrial) package: je = ceramic dual in-line, (300 mil body), 16-lead pe = plastic dip, (300 mil body), 16-lead oe = plastic soic, (300 mil body), 16-lead oe713 = plastic soic, (300 mil body), 16-lead (tape and reel) pf = plastic dip, (300 mil body), 24-lead og = plastic soic, (300 mil body), 24-lead og713 = plastic soic, (300 mil body), 24-lead (tape and reel) pj = plastic dip, (300 mil body), 28-lead oi = plastic soic, (300 mil body), 28-lead oi713 = plastic soic, (300 mil body), 28-lead (tape and reel) examples: a) TC500acoe: commercial temp., 16ld soic package. b) TC500acoe713: commercial temp., 16ld soic package, tape and reel. c) TC500acpe: commercial temp., 16ld pdip package. d) TC500aije: industrial temp., 16ld cerdip package. a) TC500coe: commercial temp., 16ld soic package. b) TC500coe713: commercial temp., 16ld soic package, tape and reel. c) TC500cpe: commercial temp., 16ld pdip package. d) TC500ije: industrial temp., 16ld cerdip package. a) tc510cog: commercial temp., 24ld pdip package. b) tc510cog713: commercial temp., 24ld pdip package, tape and reel. c) tc510cpf: commercial temp., 24ld pdip package. a) tc514coi: commercial temp., 28ld pdip package. b) tc514coi713: commercial temp., 28ld pdip package, tape and reel. c) tc514cpj: commercial temp., 28ld pdip package. data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
TC500/a/510/514 ds21428d-page 32 ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. ds21428d-page 33 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. microchip makes no representations or war- ranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2006, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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